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50 ma/500 ma, high efficiency, ultralow power step-down regulator data sheet adp5300 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2015 analog devices, inc. all rights reserved. technical support www.analog.com features input supply voltage range: 2.15 v to 6.50 v operates down to 2.00 v voltage ultralow 180 na quiescent current selectable output voltage of 0.8 v to 5.0 v 1.5% output accuracy over full temperature range in pwm mode selectable hysteresis mode or pwm operation mode output current up to 50 ma in hysteresis mode up to 500 ma in pwm mode voutok flag monitors the output voltage ultrafast stop switching control 100% duty cycle operation mode 2.0 mhz typical switching frequency in pwm mode with optional sync clock range from 1.2 mhz to 2.5 mhz quick output discharge (qod) option uvlo, ocp, and tsd protection 10-lead, 3 mm 3 mm lfcsp ?40c to +125c operating temperature range applications energy (gas and water) metering portable and battery-powered equipment medical applications keep-alive power supplies typical application circuit 2.2h sw pgnd fb 10f 10f v out pvin vid v in = 2.15 to 6.50v adp5300 r0 vid0: 1.2v vid1: 1.5v vid2: 1.8v vid3: 2.0v vid4: 2.1v vid5: 2.2v vid6: 2.3v vid7: 2.4v vid8: 2.5v vid9: 2.6v vid10: 2.7v vid11: 2.8v vid12: 2.9v vid13: 3.0v vid14: 3.3v vid15: 3.6v epad en off on pwm sync/mode hys stop stop sw voutok agnd 13366-001 figure 1. general description the adp5300 is a high efficiency, ultralow quiescent current step-down regulator that draws only 180 na quiescent current to regulate the output. the adp5300 runs from an input supply voltage range of 2.15 v to 6.50 v, allowing the use of multiple alkaline or nimh, li-ion cells, or other power sources. the output voltage is selectable from 0.8 v to 5.0 v by an external vid resistor and factory fuse. the total solution requires only four tiny external components. the adp5300 can operate between hysteresis mode and pulse- width modulation (pwm) mode via the sync/mode pin. the regulator in hysteresis mode achieves excellent efficiency at a power of less than 1 mw and provides up to 50 ma of output current. the regulator in pwm mode produces a lower output ripple and supplies up to 500 ma of output current. the flexible configuration capability during operation of the device enables very efficient power management to meet both the longest battery life and low system noise requirements. the adp5300 contains a voutok flag, which monitors the output voltage and runs at a 2 mhz switching frequency in pwm mode. sync/mode can be synchronized to an external clock from 1.2 mhz to 2.5 mhz. the adp5300 includes an stop pin that can disable the regulator switching temporarily, in this way a quiet system environment can be achieved to benefit noise sensitive circuitry, such as data conversion, rf data transmisson, and analog sensing. other key features in the adp5300 include separate enabling, qod, and safety features such as overcurrent protection (ocp), thermal shutdown (tsd), and input undervoltage lockout (uvlo). the adp5300 is available in a 10-lead, 3 mm 3 mm lfcsp rated for a ?40c to +125c operating temperature range. multifunction pin names may be referenced by their relevant function only.
adp5300 data sheet rev. 0 | page 2 of 21 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? typical application circuit ............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? detailed functional block diagram .............................................. 3 ? specifications ..................................................................................... 4 ? absolute maximum ratings ............................................................ 6 ? thermal resistance ...................................................................... 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 8 ? theory of operation ...................................................................... 14 ? buck regulator operational modes ......................................... 14 ? osillator and synchronization .................................................. 14 ? adjustable and fixed output voltages .................................... 14 ? undervoltage lockout (uvlo) ............................................... 15 ? enable/disable ............................................................................ 15 ? current limit .............................................................................. 15 ? short-circuit protection ............................................................ 15 ? soft start ...................................................................................... 15 ? startup with precharged output .............................................. 15 ? 100% duty operation ................................................................ 15 ? active discharge ......................................................................... 15 ? voutok function ................................................................... 15 ? stop switching ............................................................................ 16 ? thermal shutdown .................................................................... 16 ? applications information .............................................................. 17 ? external component selection ................................................ 17 ? selecting the inductor ................................................................ 17 ? output capacitor ........................................................................ 17 ? input capacitor ........................................................................... 18 ? efficiency ..................................................................................... 18 ? circuit board layout recommendations ............................... 18 ? typical application circuits ......................................................... 19 ? factory programmable options ................................................... 20 ? outline dimensions ....................................................................... 21 ? ordering guide .......................................................................... 21 ? revision history 9/15revision 0: initial version
data sheet adp5300 rev. 0 | page 3 of 21 detailed functional block diagram voutok mode internal feedback resistor divider soft start 90% 87% fb control logic i lim_pwm i lim_hys standby 0.808v ?0.6a (pwm) 0.8v v to i 0a (hys) 0.8v pwm driver pvin pvin sw pgnd fb 1.2v 0.4v sync mode 1.2v 0.4v pvin uvlo band gap bias and housekeeping keep alive block 2.06v 2.00v stop en sync/ mode driver pvin vid agnd 2mhz osc slope compensation 0.4v 1.2v force sleep 13366-002 figure 2.
adp5300 data sheet rev. 0 | page 4 of 21 specifications v in = 3.6 v, v out = 2.5 v, t j = ?40c to +125c for minimum and maximum specifications, and t a = 25c for typical specifications, unless otherwise noted. table 1 . parameter symbol min typ max unit test conditions/comments input supply voltage range v in 2.15 6.50 v shutdown current i shutdown 18 40 na v en = 0 v, ?40c t j +85c 18 130 na v en = 0 v, ?40c t j +125c quiescent current operating quiescent current in hysteresis mode i q_hys 180 260 na ?40c t j +85c 180 350 na ?40c t j +125c 570 1400 na 100% duty cycle operation, v in = 3.0 v, v out set to 3.3 v operating quies cent current in hysteresis mode i q - hys2 2.3 3.2 a v in = 3.6 v, v stop = 3.6 v operating quiescent current in pwm mode i q_pwm 425 630 a undervoltage lockout uvlo uvlo threshold rising v uvlo_rising 2.06 2.14 v falling v uvlo_falling 1.90 2.00 v oscillator circuit switching frequency in pwm mode f sw 1.7 2.0 2.3 mhz feedback (fb) threshold of frequency fold v osc_fold 0.3 v synchronization threshold sync clock range sync clock 1.2 2.5 mhz sync high level threshold sync high 1.2 v sync low level threshold sync low 0.4 v sync duty cycle range sync duty 100 1/f sw ? 150 ns sync/mode leakage current i sync_leakage 50 150 na v sync/mode = 3.6 v mode transition transition delay from hysteresis mode to pwm mode t hys_to_pwm 20 clock cycles sync/mode goes logic high from logic low en pin input voltage threshold high v ih 1.2 v low v il 0.4 v input leakage current i en_leakage 25 na stop switching pwm switching stop delay t stop - rise - delay 10 n s stop goes logic high from low pwm switching resume delay t stop - fal l - delay 20 n s stop goes logic low from high fb pin output options by vid resistor v out _opt 0.8 5.0 v 0.8 v to 5.0 v in various factory options pwm mode fixed vid code voltage accuracy v fb_pwm_fix ?0.6 +0.6 % t j = 25c, output voltage setting via factory fuse ?1.2 +1.2 % ?40c t j +125c adjustable vid code voltage accuracy v fb_pwm_adj ?1.5 +1.5 % output voltage setting via vid resistor
data sheet adp5300 rev. 0 | page 5 of 21 parameter symbol min typ max unit test conditions/comments hysteresis mode fixed vid code threshold accuracy from active mode to standby mode v fb_hys_fix ?0.75 +0.75 % t j = 25c ?2.5 +2.5 % ?40c t j +125c adjustable vid code threshold accuracy from active mode to standby mode v fb_hys_adj ?3 +3 % ?40c t j +125c hysteresis of threshold accuracy from active mode to standby mode v fb_hys (hys) 1 % feedback bias current i fb 66 95 na output option 0, v out = 2.5 v 25 45 na output option 1, v out = 1.3 v sw pin high - side power fet on resistance r ds (on) h 386 520 m? pin to pin measurement low - side power fet on resistance r ds (on) l 299 470 m? pin to pin measurement current limit in pwm mode i lim_pwm 800 1000 1200 ma sync/mode = high peak current in hysteresis mode i lim_hys 265 ma sync/mode = low minimum on time t min_on 40 70 ns voutok pin monitor threshold v outok (rise) 87 90 93 % monitor hysteresis v outok (hys) 3 % monitor rising delay t voutok_rise 40 s monitor falling delay t voutok_fall 10 s leakage current i voutok_leakage 0.1 1 a output low voltage v outok_low 50 80 mv i voutok = 100 a soft start default soft start time t ss 350 s factory trim, 1 bit (350 s and 2800 s) start - up delay t start_delay 2 ms delay from the en pin being pulled high c out discharge switch on resistance r dis 290 ? thermal shutdown threshold t shdn 142 c hysteresis t hys 127 c
adp5300 data sheet rev. 0 | page 6 of 21 absolute maximum ratings table 2. parameter rating pvin to pgnd ?0.3 v to +7 v sw to pgnd ?0.3 v to pvin + 0.3 v fb to agnd ?0.3 v to +7 v vid to agnd ?0.3 v to +7 v en to agnd ?0.3 v to +7 v voutok to agnd ?0.3 v to +7 v sync/mode to agnd ?0.3 v to +7 v stop to agnd ?0.3 v to +7 v pgnd to agnd ?0.3 v to +0.3 v storage temperate range ?65c to +150c operating temperature range ?40c to +125c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. jc is the thermal resistance from the operating portion of the device to the outside surface of the package (case) closest to the device mounting area. table 3. thermal resistance package type ja jc unit 10-lead, 3 mm 3 mm lfcsp 57 0.86 c/w esd caution
data sheet adp5300 rev. 0 | page 7 of 21 pin configuration and fu nction descriptions 1 en 2 stop 3 sync/mode 4 vid 5 fb 10 pvin 9sw 8pgnd 7agnd 6voutok top view (not to scale) adp5300 notes 1. the exposed pad must be soldered to a large external copper ground plane underneath the ic for thermal dissipation. 13366-003 figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 en enable input for the regulator. set to logic low to disable the regulator. 2 stop stop switching input signal. when this pin is logic high, the regulator stops the regulator switching. when this pin is logic low, the regulator resumes the regulator switching. 3 sync/mode synchronization input pin (sync). to synchronize the switching frequency of the device to an external clock, connect this pin to an external clock with a frequency from 1.2 mhz to 2.5 mhz. pwm or hysteresis mode selection pin (mode). when this pin is logic high, the regulator operates in pwm mode. when this pin is logic low, the regulator operates in hysteresis mode. 4 vid voltage configuration pin. connect an external resistor (r vid ) from this pin to ground to configure the output voltage of the regulator (see table 5). 5 fb feedback sensing input for the regulator. 6 voutok output power-good signal. this open-drain outp ut is the power-good signal for the output voltage. 7 agnd analog ground. 8 pgnd power ground. 9 sw switching node output for the regulator. 10 pvin power input for the regulator. epad exposed pad. the exposed pad must be soldered to a large external copper ground plane underneath the ic for thermal dissipation.
adp5300 data sheet rev. 0 | page 8 of 21 typical performance characteristics v in = 3.6 v, v out = 2.5 v, l = 2.2 h, c in = c out = 10 f, f sw = 2 mhz, t a = 25c, unless otherwise noted. efficiency (%) load current (ma) 100 90 80 70 60 50 40 30 0.001 0.01 0.1 1 10 v in = 2.5v v in = 3.0v v in = 3.6v v in = 4.2v v in = 5.0v v in = 6.0v 13366-004 figure 4 . hysteresis efficiency vs. load current, v out = 1.2 v efficiency (%) load current (ma) 100 90 80 70 60 50 40 0.001 0.01 0.1 1 10 v in = 2.5v v in = 3.0v v in = 3.6v v in = 4.2v v in = 5.0v v in = 6.0v 13366-005 figure 5 . hysteresis efficiency vs. load current, v out = 1.8 v efficiency (%) load current (ma) 100 90 80 70 60 50 0.001 0.01 0.1 1 10 v in = 3.6v v in = 4.2v v in = 5.0v v in = 6.0v 13366-006 figure 6 . hysteresis efficiency vs. load current, v out = 3.3 v efficiency (%) load current (ma) 100 90 80 70 60 50 40 0.001 0.01 0.1 1 10 v in = 2.5v v in = 3.0v v in = 3.6v v in = 4.2v v in = 5.0v v in = 6.0v 13366-007 figure 7 . hysteresis efficiency vs. load current, v out = 1.5 v efficiency (%) load current (ma) 100 90 80 70 60 50 0.001 0.01 0.1 1 10 v in = 3.6v v in = 3.0v v in = 4.2v v in = 5.0v v in = 6.0v 13366-008 figure 8 . hysteresis efficiency vs. load current, v out = 2.5 v efficiency (%) load current (ma) 0 10 20 30 40 50 60 70 80 90 100 0 100 200 300 400 500 v in = 2.5v v in = 3.0v v in = 3.6v v in = 4.2v v in = 5.0v v in = 6.0v 13366-009 figure 9 . pwm efficiency vs. load current, v out = 1.2 v
data sheet adp5300 rev. 0 | page 9 of 21 efficiency (%) load current (ma) 0 10 20 30 40 50 60 70 80 90 100 0 100 200 300 400 500 v in = 2.5v v in = 3.0v v in = 3.6v v in = 4.2v v in = 5.0v v in = 6.0v 13366-010 figure 10 . pwm efficiency vs. load current, v out = 1.5 v efficiency (%) load current (ma) 0 10 20 30 40 50 60 70 80 90 100 0 100 200 300 400 500 v in = 3.0v v in = 3.6v v in = 4.2v v in = 5.0v v in = 6.0v 13366-0 1 1 figure 11 . pwm efficiency vs. load current, v out = 2.5 v shutdown current (na) v in (v) 0 20 40 60 80 100 120 140 160 2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5 ?40oc +25oc +85oc +125oc 13366-012 figure 12 . shutdown current vs. v in , en = low efficiency (%) load current (ma) 0 10 20 30 40 50 60 70 80 90 100 0 100 200 300 400 500 v in = 3.0v v in = 3.6v v in = 4.2v v in = 5.0v v in = 6.0v v in = 2.5v 13366-013 figure 13 . pwm efficiency vs. load current, v out = 1.8 v efficiency (%) load current (ma) 0 10 20 30 40 50 60 70 80 90 100 0 100 200 300 400 500 v in = 3.6v v in = 4.2v v in = 5.0v v in = 6.0v 13366-014 figure 14 . pwm efficiency vs. load current, v out = 3.3 v quiescent current (na) v in (v) 2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5 ?40oc +25oc +85oc +125oc 100 150 200 250 300 350 13366-015 figure 15 . hysteresis quiescent current vs. v in , sync/mode = low
adp5300 data sheet rev. 0 | page 10 of 21 feedback voltage (mv) temperature (c) 797 798 799 800 801 ?40 25 85 125 13366-016 figure 16 . feedback voltage vs. temperature, pwm mode high-side r ds (on) h (m) v in (v) 2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5 100 200 300 400 500 600 700 ?40oc +25oc +125oc 13366-017 figure 17 . high - side r ds (on) h vs. v in peak current limit (ma) temperature (c) ?40 25 85 125 840 890 940 990 1040 1090 13366-018 figure 18 . peak current limit vs. temperature feedback voltage (mv) temperature (c) ?40 25 85 125 792 794 796 798 800 802 804 806 808 810 active to standby standby to active 13366-019 figure 19 . feedback voltage vs. temperature, hysteresis mode low-side r ds (on) l (m) v in (v) 2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5 ?40oc +25oc +125oc 100 150 200 250 300 350 400 13366-020 figure 20 . low - side r ds (on) l vs. v in peak current limit (ma) v in (v) 2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5 800 850 900 950 1000 1050 1100 1150 1200 ?40oc +25oc +125oc 13366-021 figure 21 . peak current limit vs. v in
data sheet adp5300 rev. 0 | page 11 of 21 uvlo threshold (v) temperature (c) ?40 25 85 125 1.96 1.98 2.00 2.02 2.04 2.06 2.08 2.10 rising falling 13366-022 figure 22 . uvlo threshold, rising and falling vs. temperature ch4 140m a 4 1 2 ch2 2.00v ch4 500m a ch1 100mv m 200 s a t 39.60% v out i l sw 13366-023 figure 23 . steady waveform of hysteresis mode, i load = 1 ma (i l is the inductor current) ch1 1.22v 2 1 3 4 ch2 5.00v ch4 500m a ch1 1.00v m 200 s a t 50.60% ch3 2.00v v in v out i l sw 13366-024 figure 24 . soft start, i load = 300 ma (i l is the inductor current) switching frequency (khz) v in (v) 2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5 1.7 1.8 1.9 2.0 2.1 2.2 2.3 ?40oc +25oc +125oc 13366-025 figure 25 . switching frequency vs. v in ch2 2.72v 2 1 4 ch2 2.00v ch4 200m a ch1 10.0mv m 400 n s a t 90.60% v out (ac) i l sw 13366-026 figure 26 . steady waveform of pwm mode, i load = 300 ma (i l is the inductor current) 2 1 4 v out v in i l sw ch1 1.05v ch2 5.00v ch4 500m a ch1 500mv m 100 s a t 40.00% ch3 2.00v 13366-027 figure 27 . soft start with precharge function (i l is the inductor current)
adp5300 data sheet rev. 0 | page 12 of 21 1 4 v out (ac) i out ch4 11 1m a ch4 50.0m a ch1 50.0mv m 200 s a t 20.80% 13366-028 figure 28 . load transient of hysteresis mode, i load from 0 ma to 50 ma 1 2 4 v out (ac) v in i l sw ch3 4.72v ch2 5.00v ch4 500m a ch1 50.0mv m 2.00 ms a t 30.00% ch3 2.00v 13366-029 figure 29 . line transient of hysteresis mode, i load = 10 a (i l is the inductor current) 1 4 v out v in i l ch3 4.80v ch4 200m a ch1 1.00v m 10.0 ms a t 40.20% ch3 1.00v 13366-030 figure 30 . input voltage ramp u p and ramp d own in hysteresis mode (i l is the inductor current) 1 4 v out (ac) i out ch4 308m a ch4 200m a ch1 50.0mv m 200 s a t 20.40% 13366-031 figure 31 . load transient of pwm mode, i load from 125 ma to 375 ma 1 2 3 4 v out (ac) v in i l sw ch3 4.28v ch2 5.00v ch4 500m a ch1 10.0mv m 2.00 m s a t 30.20% ch3 2.00v 13366-032 figure 32 . line transient of pwm mode, i load = 500 ma (i l is the inductor current) 1 3 2 v out voutok sw ch1 1.32v ch2 2.00v ch1 1.00v m 200 s a t 40.00% ch3 1.00v 13366-033 figure 33 . voutok function
data sheet adp5300 rev. 0 | page 13 of 21 1 4 2 v out i l sw ch1 1.44v ch2 2.00v ch1 2.00v m 10.0 s a t 40.20% ch4 500m a 13366-034 figure 34 . output short protection (i l is the inductor current) sync/ mode sw ch2 1.40v ch2 2.00v ch1 2.00v m 400 n s a t 50.00% 1 2 13366-035 figure 35 . synchronized to 2.5 mhz v out sync/mode sw ch3 1.56v ch2 2.00v ch1 100mv ch3 2.00v b w m 20.0 s a t 39.80% 3 1 2 13366-136 figure 36 . hysteresis mode to pwm mode with 10 ma load current v out i l sw ch1 1.44v ch2 2.00v ch1 2.00v m 1.00 ms a t 40.20% ch4 500m a 4 1 2 13366-036 figure 37 . output short recovery (i l is the inductor current) 3 1 2 en v out sw ch3 1.64v ch2 2.00v ch1 1.00v m 4.00 ms a t 40.00% ch3 2.00v 13366-037 figure 38 . quick output discharge function v out v stop sw ch3 520mv ch2 2.00v ch1 2.00v b w ch3 2.00v b w m 100ms a 3 1 2 13366-137 figure 39 . stop switching function
adp5300 data sheet rev. 0 | page 14 of 21 theory of operation the adp5300 is a high efficient, ultralow quiescent current , step - down regulator in a 10 - lead lfcsp package to meet demanding performance and board space requirements. the device enables direct connection to a wide input voltage range of 2.15 v to 6.50 v , allowing the use of multiple a lkaline /nimh or , li - ion cells and other power sources. buck regulator opera tional modes pwm mode in pwm mode, the buck regulator in the adp5300 o perates at a fixed frequency that is set by an internal oscillator. at the star t of each oscillator cycle, the high - side mosfet switch turns on and sends a positive voltage across the inductor. the inductor current increases until the current sense signal exceeds the peak inductor current threshold, which turns off the high - side mosf et s witch. this threshold is set by the error amplifier output. during the high - side mosfet off time, the inductor current decreases through the low - side mosfet until the next oscillator clock pulse starts a new cycle. hysteresis mode in h ysteresis mode, the buck regulator in the adp5300 charges the output voltage slightly higher than its nominal output voltage with pwm pulses by regulating the constant peak inductor current. whe n the output voltage increases until the output sense signal exceeds the hysteresis upper threshold, the regulato r enters standby mode. in standby mode, the high - side and low - sid e mosfets and a majority of the circuitry are disabled to allow a low quiescen t current as well as high efficiency performance. during standby mode, the output capacitor supplies energy into the load , and the output voltage decreases until it falls below the hysteresis comparator lower threshold. the buck regulator wakes up and generates the pwm pulses to charge the output again. because the output voltage occasionally enters standby mode and then rec overs, the output voltage ripple in hysteresis mode is larger than the ripple in pwm mode. m ode selection the adp5300 includes the sync/mode pin to allow flexible configuration in hysteresis mo de or pwm mode. when a logic high level is applied to the sync/mode pin, the buck regulator is forced to operate in pwm mode. in pwm mode , the regulator can supply up to 500 ma of output current. the regulator can provide lower output ripple and output no ise in pwm mode, which is useful for noise sensitive applications. when a logic low level is applied to the sync/mode pin, the buck regulator is forced to operate in hysteresis mode. in hysteresis mode, the regulator draws only 180 na of quiescent current typical to regulate the output under zero load, which allows the regulator to act as a keep - alive power supply in a battery - powered system. in hysteresis mode, the regulator supplies up to 50 ma of output current with a relatively large output ripple compa red to pwm mode. the user can alternate between hysteresis mode and pwm mode during operation. the flexible configuration capability during operation of the device enables efficient power management to meet high efficiency and low output ripple requiremen ts when the system switches between active mode and standby mode. osillator and synchronization the adp5300 operates at a 2 mhz switching frequency typical in pwm operation mode. the switching f requency of the adp5300 can be synchronized to an external clock with a frequency range from 1.2 mhz to 2.5 mhz. the adp5300 automat ically detects the presence of an external clock applied to the sync/mode pin, and the switching frequency transitions to the frequency of the external clock. when the external clock signal stops, the device automatically switches back to the internal cloc k. adjustable and fixed output voltages the adp5300 provides adjustable output voltage settings by connecting one resistor through the vid pin to agnd. the vid detection circuitry works in the start - up period, and the voltage id code is sampled and held in the internal register and does not change until the next power recycle. furthermore, the adp5300 provides a fixed output voltage programmed via the factory fuse. in this condition, connect the vid pin to the pvin pin. for the output voltage sett ings, the feedback resistor divider is built into the adp5300 , and the feedback pin (fb) must be tied directly to the output. an ultralow power voltage reference and an integrated high impedance (50 m typical) feedback divider network contribute to the low quiescent current. table 5 lists the output voltage options by the vid pin configu rations. a 1 % accuracy resistor through vid to ground is recommended. table 5 . output voltage (v out ) options by the vid p in v out (v) vid configuration factory option 0 factory option 1 short to g round 3.0 3.1 short to pvin 2.5 1.3 r vid = 499 k? 3.6 5.0 r vid = 316 k? 3.3 4.5 r vid = 226 k? 2.9 4.2 r vid = 174 k? 2.8 3.9 r vid = 127 k? 2.7 3.4 r vid = 97.6 k? 2.6 3.2 r vid = 76.8 k? 2.4 1.9 r vid = 56.2 k? 2.3 1.7 r vid = 43 k? 2.2 1.6 r vid = 32.4 k? 2.1 1.4 r vid = 25.5 k? 2.0 1.1 r vid = 19.6 k? 1.8 1.0 r vid = 15 k? 1.5 0.9 r vid = 11.8 k? 1.2 0.8
data sheet adp5300 rev. 0 | page 15 of 21 undervoltage lockout (uvlo) the undervoltage lockout circuitry monitors the input voltage level on the pvin pin. if the input voltage falls below 2.00 v (typical), the regulator turns off. after the input voltage rises above 2.0 6 v (typical), the soft start period initiate s , and when the en pin is high, the regulator enable s. e nable /d isable the adp5300 includes a separate enable (en) pin. a logic high on the e n pin starts the regulator. due to the low quiescent current design, it is typical for the regulator to start switching after a delay of a few milliseconds from the en pin being pulled high. a logic low on the en pin immediately disables the regulator and brings the regulator into extremely low current consumption . current limit the buck regulators in the adp 5300 ha ve protection circuitry that limits the direction and the amount of current to a certain level that flows through the high - side mosfet and the low - side mosfet in cycle - by - cycle mode. the positive current limit on the high - side mosfet limits the amou nt of current that can flow from the input to the output. the negative current limit on the low - side mosfet prevents the inductor current from reversing direction and flowing out of the load. short - circuit protection the buck regulators in the adp5300 include frequency foldback to prevent current runaway on a hard short. when the output voltage at the feedback (fb) pin falls below 0.3 v typical, indicating the possibility of a hard short at the o utput, the switching frequency (in pwm mode) is reduced to one - fourth of the internal oscillator frequency. the reduction in the switching frequency allows more ti me for the inductor to discharge, preventing a runaway of output current. soft start the adp5300 has an internal soft start function that ramps up the output voltage in a controlled manner upon startup, thereby limiting the inrush current. this feature prevents possible input voltage dr ops when a battery or a high impedance power source is connected to the input of the device. the default typical soft start time is 350 s for the regulator. a different soft start time (2800 s) can be programmed for adp5300 by the factory fuse. startup with prechar ged output th e buck regulators in the adp5300 include a precharged start - up feature to protect the low - side mosfet from damage during startup. if the output voltage is precharged before the regulator turns on, the regulator prevents reverse inductor current , which discharges the output capacitor , until the internal soft start ref erence voltage exceeds the precharged voltage on the fb pin. 100% duty operation when the input voltage approaches the output voltage, the adp5300 stops switching and enters 100% duty cycle oper ation . it connects the output via the inductor and the internal high - side power switch to the input. when the input voltage is charged again and the required duty cycle falls to 95% typical, the buc k immediately restarts switching and regulation without al lowing overshoot on the output voltage. in hysteresis mode, the adp5300 draws an ultralow quiescent current of only 570 na typical during 100% duty cycle operation . active discharge the regulat or in the adp5300 integrates an optional, factory programmable discharge switch from the switching node to ground. this switch turns on when its associated regulator is disabled, which helps discharge the output capacitor quickly. the typical value of the discharge switch is 290 ? for the regulator. by default, the discharge function is not enabled. the factory fuse can enable the active disc harge function. voutok function the adp5300 includes an open - drain , power - good output (voutok pin) that is active high when the buck regulator operat es normally. by default, the voutok pin monit ors the output voltage. a logic high on the voutok pin indicates that the regulated output voltage of the buck regulator is above 90% (typical) of its nominal output. when the regulated output volta ge of the buck regulator falls below 87% (typical) of its nominal output for a delay time greater than approximately 10 s, the voutok pin goes low.
adp5300 data sheet rev. 0 | page 16 of 21 s top s witching the adp5300 includes a stop input pin (stop) that can temporarily stop the r egulator switching in hysteresis mode. when a logic high level is applied to the stop pin, the buck regulator is forced to stop switching immediately. when a logic low level is applied to the stop pin, the buck regulator resumes switching. note that tens of nanoseconds delay time exists from when the stop signal goes high to fully stop switching. in some battery - powered system s , the microcontroller unit ( mcu ) can command the regulator to stop switching via the stop signal, and the regulator then relies on the output capacitor to supply the load. i n this period, a quie t system environment can be achieved which benefit s the noise sensitive circuitry, such as data conversion, rf data transmi ssion , and analog sens ing . after the noise sensitive circuitry comple tes its task, the mcu can control the regulator and resume switching regulation mode. if needed, the voutok signal can monitor the output voltage in the event it dips too low to latch up the system. figure 40 shows the stop switching operation status in adp5300 . when the regulator is enabled with en pin pulled high, t he stop signal control is valid, and when en pin is logic low, the stop signal is ignored. dc to dc output output load dc to dc switching stop signal 2a 2.500v 2.540v 2.175v to voutok threshold voutok flag 13366-040 10ms of ma figure 40 . stop switching operation status thermal shutdown if the adp5300 junction temperature exceeds 142c, the thermal shutdown circuit turns off the ic except for the internal linear regulator. extreme junction temperatures can be t he result of high current operation, poor circuit board design, or high ambient temperature. a 15c hysteresis is included so that the adp5300 does not return to operation after thermal shutdown until the junction temperature falls below 127c. when the device exits thermal shutdown, a soft start initiate s for each enabled channel.
data sheet adp5300 rev. 0 | page 17 of 21 applications information this section describes the external components selection for the adp5300 . the typical application circuit is shown in figure 41. 2.2h sw pgnd fb 10f mlcc 10f mlcc v out = 1.8v pvin en vid v in = 2.15v to 6.50v adp5300 voutok epad sync/mode stop agnd r2 1m ? r1 19.6k ? 13366-041 figure 41. typical application circuit external component selection the adp5300 is optimized for operation with a 2.2 h inductor and 10 f output capacitors for various output voltages using the closed-loop compensation and adaptive slope compensation circuits. the selection of components depends on the efficiency, the load current transient, and other application requirements. the trade-offs among performance parameters, such as efficiency and transient response, are made by varying the choice of external components. selecting the inductor the high switching frequency of the adp5300 allows the use of small surface-mount power inductors. the dc resistance (dcr) value of the selected inductor affects efficiency. in addition, it is recommended to select a multilayer inductor rather than a magnetic iron inductor because the high switching frequency increases the core temperature rise and enlarges the core loss. a minimum requirement of the dc current rating of the inductor is for it to be equal to the maximum load current plus half of the inductor current ripple (i l ), as shown by the following equations: ? ? ? ? ? ? ? ? ? ? ? ? ? ?? sw in out out l fl v v vi C1 ? ? ? ? ? ? ? ? 2 l load(max) pk i ii use the inductor series from the different vendors shown in table 6. output capacitor output capacitance is required to minimize the voltage overshoot, the voltage undershoot, and the ripple voltage present on the output. capacitors with low equivalent series resistance (esr) values produce the lowest output ripple. furthermore, use capacitors such as x5r and x7r dielectric capacitors. do not use y5v and z5u capacitors, because they are unsuitable choices due to their large capacitance variation over temperature and their dc bias voltage changes. because esr is important, select the capacitor using the following equation: l ripple cout i v esr ? ? where: esr cout is the esr of the chosen capacitor. v ripple is the peak-to-peak output voltage ripple. increasing the output capacitor value has no effect on stability and may reduce output ripple and enhance load transient response. when choosing the output capacitor value, it is important to account for the loss of capacitance due to output voltage dc bias. use the capacitor series from the different vendors shown in table 7. table 6. recommended inductors vendor model inductance (h) dimensions (mm) dcr (m) i sat 1 (a) tdk mlp2016v2r2mt0s1 2.2 2.0 1.6 0.85 280 1.0 wurth 74479889222 2.2 2.5 2.0 1.2 250 1.7 coilcraft lps3314-222mr 2.2 3.3 3.3 1.3 100 1.5 1 i sat is the dc current at which the inductance drops 30% (typical) from its value without current. table 7. input and output capacitors vendor model capacitance (f) size murata grm188d71a106ma73 10 0603 murata grm21br71a106ke51 10 0805 murata grm31cr71a106ka01 10 1206
adp5300 data sheet rev. 0 | page 18 of 21 input capacitor an input capacitor is required to reduce the input voltage ripple, input ripple current, and source impedance. place the input capacitor as close as possible to the pvin pin. a low esr x7r or x5r capacitor is highly recommended to minimize the input voltage ripple. use the following equation to determine the rms input current: ?? in out in out max load rms v vvv ii ? ? )( for most applications, a 10 f capacitor is sufficient. the input capacitor can be increased without any limit for improved input voltage filtering. efficiency efficiency is the ratio of output power to input power. the high efficiency of the adp5300 has two distinct advantages. first, only a small amount of power is lost in the dc-to-dc converter package, which in turn reduces thermal constraints. second, the high efficiency delivers the maximum output power for the given input power, thereby extending battery life in portable applications. power switch conduction losses power switch dc conduction losses are caused by the flow of output current through the high-side, p-channel power switch and the low-side, n-channel synchronous rectifier, which have internal resistances (r ds (on) ) associated with them. the amount of power loss is approximated by p sw_cond = ( r ds (on) h d + r ds (on) l (1 ? d )) i out 2 where: in out v v d ? the internal resistance of the power switches increases with temperature and with the input voltage decrease. inductor losses inductor conduction losses are caused by the flow of current through the inductor, which has an internal dcr associated with it. larger size inductors have smaller dcr, which can decrease inductor conduction losses. inductor core losses relate to the magnetic permeability of the core material. because the adp5300 is a high switching frequency dc-to-dc regulator, shielded ferrite core material is recommended because of its low core losses and low electromagnetic interference (emi). to estimate the total amount of power lost in the inductor, use the following equation: p l = dcr i out 2 + core losses driver losses driver losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. each time a power device gate is turned on and turned off, the driver transfers a charge from the input supply to the gate, and then from the gate to ground. estimate driver losses using the following equation: p driver = ( c gate_h + c gate_l ) v in 2 f sw where: c gate_h is the gate capacitance of the internal high-side switch. c gate_l is the gate capacitance of the internal low-side switch. f sw is the switching frequency in pwm mode. the typical values for the gate capacitances are 69 pf for c gate_h and 31 pf for c gate_l . transition losses transition losses occur because the p-channel switch cannot turn on or turn off instantaneously. in the middle of a switch node transition, the power switch provides all of the inductor current. the source to drain voltage of the power switch is half of the input voltage, resulting in power loss. transition losses increase with both load current and input voltage and occur twice for each switching cycle. use the following equation to estimate transition losses: p tran = v in /2 i out ( t r + t f ) f sw where: t r is the rise time of the sw node. t f is the fall time of the sw node. the typical value for the rise and fall times, t r and t f , is 2 ns. circuit board layout recommendations 10f 10v/xr5 0603 10f 6.3v/xr5 0603 l1?2.2h 0603 adp5300 top view 5.7 4.6 13366-042 figure 42. typical pcb layout
data sheet adp5300 rev. 0 | page 19 of 21 typical application circuits the adp5300 can be used as a keep-alive, ultralow power step- down regulator to extend the battery life (see figure 43), and as a battery-powered equipment or wireless sensor network controlled by a microcontroller or a processor (see figure 44). the stop switching function can achieve a quiet system environment for a noise sensitive application. 2.2h sw pgnd fb 10f r1 1m ? 10f v out = 3.0v adc/rf/afe mcu (always on) pvin vid en sync/mode v in = 3.0v to 4.2v adp5300 voutok agnd stop li-ion battery 13366-043 figure 43. typical adp5300 application with li-ion battery and stop switching functionality 2.2h sw pgnd fb 10f r1 1m ? 10f v out = 3.0v adc/rf/afe mcu (always on) pvin vid en sync/mode v in = 2.0v to 3.0v adp5300 voutok agnd stop two alkaline or nimh batteries r1 19.6k ? 1% 13366-044 figure 44. typical adp5300 application with two alkaline/nimh batteries
adp5300 data sheet rev. 0 | page 2 0 of 21 factory programmable option s to order a device with options other than the default options, contact your local analog devices sales or distribution representative . table 8 . output voltage vid settin g options option description option 0 vid resistor to set the output voltage as: 1.2 v, 1.5 v, 1.8 v, 2.0 v, 2.1 v, 2.2 v, 2.3 v, 2.4 v, 2.5 v, 2.6 v, 2.7 v, 2.8 v , 2.9 v, 3.0 v, 3.3 v, 3.6 v, or 3.3 v (default). option 1 vid resistor to set the output voltage as: 0.8 v, 0.9 v, 1.0 v, 1.1 v, 1.3 v, 1.4 v, 1.6 v, 1.7 v, 1.9 v, 3.1 v, 3.4 v, 3.9 v , 4.2 v, 4.5 v, or 5.0 v. table 9 . output discharge functionality options option description option 0 output discharge function disabled for buck regulator (default) option 1 output discharge function enabled form buck regulator table 10 . soft - start timer options option description option 0 350 s (default) option 1 2800 s
data sheet adp5300 rev. 0 | page 21 of 21 outline dimensions 2.48 2.38 2.23 0.50 0.40 0.30 10 1 6 5 0.30 0.25 0.20 pin 1 index area seating plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pad 3.10 3.00 sq 2.90 p i n 1 i n d i c a t o r ( r 0 . 1 5 ) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 0 2-05-2013- c top view bottom view 0.20 min figure 45. 10-lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm, very very thin, dual lead (cp-10-9) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adp5300acpz-1-r7 ?40c to +125c 10-lead lead frame chip scale package [lfcsp_wd] with output discharge cp-10-9 adp5300acpz-2-r7 ?40c to +125c 10-lead lead frame chip scale package [lfcsp_wd] without output discharge cp-10-9 ADP5300-EVALZ evaluation board 1 z = rohs compliant part. ?2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d13366-0-9/15(0)

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